DARPA Chip Effort Advances AI Hardware
The Defense Advanced Research Projects Agency’s Electronics Resurgence Initiative (ERI) includes development efforts aimed at AI hardware components needed to provide the computational horsepower for accelerating the movement of big data used in emerging machine learning applications.
“U.S. leadership in microelectronics is essential to U.S. leadership in artificial intelligence,” Gilman Louie, a member of the National Security Commission on Artificial Intelligence (NSCAI), told this week’s virtual ERI conference. Maintaining the lead in AI hardware requires “technical feats only DARPA would attempt.”
In a series of reports to Congress, the commission has emphasized continued U.S. leadership in microelectronics as a way to “get AI right,” said Louie, founder and former CEO of In-Q-Tel, the venture arm of the U.S. intelligence community.
NSCAI, which is led by former Google CEO Eric Schmidt, was created last year with a three-year mandate to advance AI, machine learning and associated technologies for U.S. national security.
The commission, Louie said, sees AI technology as a “four-part stack” consisting of algorithms, data, talent and hardware. “Hardware is critical because AI algorithms increasingly rely on computational power, moving data at high speed.”
At the same time, the U.S. lead in microelectronics is eroding while the resilience of U.S. semiconductor supply chains is declining, Louie warned.
The NSCAI has proposed expanding a U.S. Navy-led project called SHIP, for State-of-the-art, Heterogeneous Integration Program. Among the Navy contractors are Intel’s federal unit and Xilinx. The prototyping effort would demonstrate AI hardware that incorporates multi-chip packaging technology.
The commission has called for chips efforts aimed at advancing process technologies beyond standard CMOS technology for national security applications. It also urged more research into 3D chip staking, photonics, carbon nanotubes, gallium nitride transistors and cryogenic computing.
The AI commission recently recommended increasing annual funding for ERI to $500 million as well as creation of a national microelectronics strategy that would underpin AI development. Those efforts would be supplemented by a proposed national microelectronics laboratory and incubator for developing AI hardware.
Those proposals were adopted in the recently approved National Defense Authorization Act currently moving through Congress.
Among the ERI efforts targeting AI applications is FRANC, for Foundations Required for Novel Compute. Among the topology approaches being pursued is breaking the traditional separation of processors and memory components to boost processing performance for applications limited by size, weight and power, including edge AI.
Along with new architectures, FRANC is also exploring non-volatile storage and “memory-centric computing devices,” according to a program summary.
“If these breakthroughs succeed, it would be tremendous for our military advantage, especially in edge AI,” said Louie.